The present invention relates to a matrix display apparatus such as a liquid crystal display or a plasma display, and in particular to a display data supply circuit used for the matrix display apparatus.
In a color liquid crystal display apparatus, three rasters or three lines corresponding to three primary colors comprising Red, Green and Blue represent one horizontal row on a display unit as described in JP-A-56-92592. Data are written into a liquid crystal panel one raster or one line at a time. For displaying one now on the display unit, therefore, it is necessary to temporarily store inputted R, G and B color display data into a memory and supply separately the stored color display data to the liquid crystal display panel one raster or one line at a time (in other words, color by color). The number of horizontal display dots of a supply source for supplying these display data must be equal to the number of horizontal display dots in the liquid crystal display panel. When the supply source of display data was changed and the number of horizontal display dots was changed, therefore, the read address generator circuit had to be changed so as to generate as many addresses as the new number of dots supplied from the source.
In order to facilitate understanding the concept of the present invention, a liquid crystal display apparatus derived by the present inventors in the course of obtaining the present invention will now be described in detail by referring to FIGS. 1 to 3.
FIG. 1 shows a row memory write and read section in the color liquid crystal display apparatus.
After display data fed from a data supply source are latched in a latch 5, the display data are stored into a row memory 7, read out from the row memory in accordance with an address supplied from a read address generator 16, and supplied to a liquid crystal panel connected to an output terminal 20. The output data supplied to the liquid crystal panel are selected in the order of Red, Green and Blue, supplied to an X-driver circuit, and written into the liquid crystal panel one line at a time.
On the basis of a display timing signal 3 and a horizontal synchronizing signal 4, a timing signal generator produces a write start signal 10 for starting to write data into the memory 7 and a read start signal 11 for starting to read data from the RAM 7 as shown in FIG. 3.
A write/read signal 9 is a signal which changes alternately to a "high" level and a "low" level by using rise timing of a dot clock 2 according to the variation of the horizontal synchronizing signal 4. The write start signal 10 is a signal generating a "high" level pulse when the display timing signal 3 has become a "high" level. The read start signal 11 is a signal generating a "high" level pulse by using a falling edge of a read clock 15 after the horizontal synchronizing signal 4 has been inputted (i.e., after the horizontal synchronizing signal 4 has become low.
A write address signal 13 fed from write address generator means 12 is cleared by the write start signal 10 and generates a write address 13 which counts up upon each rising edge of a dot clock 2. In order to perform the read operation three times during one horizontal interval, an oscillator 14 generates a read clock 15 having a period equivalent to one third of that of the dot clock 2.
A read address signal 17 fed from read address generator means 16 is cleared by the read start signal 11 to count up upon each rising edge of the read clock 15. When a write/read signal 9 is a "high" level, switch means 18 outputs the write address 13 onto an address 19 of the RAM 7. When a write/read signal 9 is a "low" level, the switch means outputs the read address 17 onto the address 19 of the RAM 7.
FIG. 2 is an internal block diagram of the above described read address generator means 16. The read address generator means 16 comprises a counter 21, a NOR circuit and an AND circuit 23. The number of horizontal display dots is arbitrarily decided according to the size of the display panel and is, say, 640 dots. Supposing that the number of horizontal display dots is 4 in order to make the description of drawings easily understandable, operation of the circuit will be hereafter described in detail. When the counter 21 in the read address generator means 16 outputs a count equivalent to 3 = (the number of horizontal display dots) - 1, the AND circuit 23 outputs a "high" level, which resets the counter 21 via the NOR circuit 22. While as many read clocks as horizontal display dots are being applied, therefore, the read address 17 of FIG. 1 makes a round. As understood from FIG. 2, it is necessary in this circuit to change the logic state of input terminals of the AND circuit 23 according to the number of horizontal display characters.
FIG. 3 is a timing chart showing the operation of the circuit shown in FIG. 1.
The operation of the circuit shown in FIG. 1 will now be described by referring to FIG. 3.
Input data 1 are latched by latch means 5 upon each rising edge of the dot clock 2 (FIG. 3E). These latched data 6 are supplied to data input terminals of the RAM 7.
When the display timing signal 3 becomes a "high" level at each of points A and B, the timing signal generator means 8 makes the write start signal 10 a "high level". Upon a succeeding falling edge of the dot clock 2, the timing signal generator means 8 makes the write start signal 10 a "low" level. The write address generator means 12 is thus reset.
Whenever the dot clock rises, the write address generator means 12 counts up addresses. In this way, the write address 13 is successively increased by the dot clock 2.
While at this time the write/read signal 9 is a "high" level corresponding to one horizontal interval, the RAM 7 is brought into the write mode. At the same time, the write address 13 is outputted on the address 19 and supplied to address terminals of the RAM 7 by the switch means 18. The latch data 6 are successively written into the RAM 7 until the write/read signal 9 becomes the "low" level.
On the other hand, the timing generator means 8 generates the read start signal 11. Upon rise timing of the read clock, the read address generator means 16 is reset. After the read address generator means 16 has been reset, the read address generator means 16 counts up the read clocks 15 and outputs the read address 17. Corresponding to the next horizontal interval, the write/read signal 9 becomes the "low" level and hence the RAM 7 is brought into the read mode. Along therewith, the read address 17 is outputted onto the address 19 and supplied to the address specifying terminals of the RAM 7. During every other horizontal interval, signals corresponding to the latch data 6 written into the RAM 7 during the previous horizontal interval are successively read out as output data 20.
In this case, the read clock 15 has a period equivalent to one third of that of the dot clock 2. In addition, the read address generator means 16 is reset by an address preset in the AND circuit 23 because of the configuration shown in FIG. 2. Therefore, display data R, G and B and data X which are not displayed on the liquid crystal display device during one horizontal interval are read from the RAM 7.
In the configuration described above, a counter so fixed as to make a round while counting a predetermined number of horizontal display dots is used. When the connected supply source is changed and the number of display dots is changed, therefore, the read address generator circuit must be changed.